NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer.
As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-
to-end security & privacy and smart connected solutions markets.
For our fast-growing product line Drivers and Energy Systems, we are currently looking for a candidate for a digital verification leader position to own the digital functional verification of our mixed-
signal circuit designs in automotive platforms. Successful applicants will be responsible for :
Studying the specification of the device under test
Defining the test specification in closed collaboration with design leaders, verification architect and product definers
Defining the digital verification planning to reach 100% functional coverage prior tapeout
Developing the UVM simulation environment (drivers, monitors, checkers and assertions) and bridge it with mixed signal verification
Developing and running digital and top-level simulations according to the verification plan
Preparing and holding design verification reviews
Creating and maintaining regression test suites
Reporting bugs, proposing solutions and following their resolution
Mentoring verification engineers on UVM methodology implementation
Leading digital verification team on projects
You will work closely with analog and digital designers as well as test and validation engineers to support both pre-silicon verification and post-
silicon validation. This is an opportunity for a skilled verification engineer to take the next step into leadership.
Your Profile : Required
Strong experience on digital verification methodologies (MDV, formal)
Strong experience writing verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews
Understand and debug digital RTL
Working knowledge of state of the art EDA tools : Cadence Incisive, Cadence Vmanager
Strong background in design and verification languages and methodologies (Verilog, SystemVerilog, UVM, SVA).
Experience in configuration database management (DesignSync, Git, SVN)
Solid scripting skills (Python preferred or Perl or TCL).
10+ years' experience verifying digital or mixed-signal ASICs
Good communication skills (both French and English)
Experience in promoting verification methodology and strategies to different teams spread across different continents
Experience in formal verification (SVA, PSL, Jasper)
Experience with mixed signal (analog, digital) verification methodologies
Experience developing behavioral models for analog IPs (both event-driven / WREAL and conservative / Verilog AMS)
Understand and debug analog schematics
Tools : Cadence Virtuoso, Collabnet, Jenkins
NXPis an Equal Opportunity / Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and / or expression, marital status, status as a disabled veteran and / or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law.
In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.