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This staff level engineer will have immediate responsibility for the development of leading edge high-level synthesis (HLS) technology.
Primary responsibilities will be the development of high quality software, which enables synthesis of algorithms written in C++ or SystemC to RTL VHDL / Verilog.
This position will focus on enhanced synthesis and verification techniques to target the product to make best use of upcoming FPGA and ASIC technologies and deliver efficient designs for both power and area.
The candidate will need a high level of expertise in this application area, will be expected to be a highly productive individual contributor, and will need to integrate well into the rest of the cohesive development team.
Work will be mostly in C++ on Linux platforms.
Computer Science or Electrical Engineering M.S. degree with 8 years’ experience or Ph.D. degree with 5 years of experience with an appreciation of hardware design and verification.
Solid programming skills and knowledge of C++ is required.
Ph.D.'s with targeted Synthesis or Verification research experience is highly desirable.
Good communication and solid software engineering skills and knowledge of C++ is required.
In depth experience of high-level synthesis modelling and verification of high-level synthesis transformations are required.
Understanding of VHDL, Verilog, RTL Synthesis tools and Mentor Graphics' tools a plus!