Exciting new opportunity with a leading developer of SOC FPGAs, based in the beautiful city of Paris.
Your mission will be to set up / define & develop a new UVM verification environment, so this is an excellent opportunity to really make it your own!
Responsibilities will also include :
recruitment and mentoring of new engineers to build the team
defining verification strategy and developing
Reviewing design specifications at both IP level and SoC level
Degree in Electronics or similar field
Circa 10 years' verification experience
RTL design / coding skills with System Verilog / VHDL
Excellent understanding of UVM processes - creating test benches from scratch
Fluent English skills
Knowledge of SOC architecture and corresponding protocols - AXI / AHB / APB
Good scripting skills - Tcl, Shell, Python
MUST BE ELIGIBLE TO WORK IN FRANCE*