Analog BE Design Engineer M/F
Grenoble, France
il y a 2j

Job description

The team is searching for a self-motivating, passionate electrical engineer for the role of Analog BE Design Engineer. As a team, we will be working on the leading-edge technology nodes to build elite custom eNVM IPs working for SMD & MCD Divisions.

You will become part of a hands-on development team that fosters engineering excellence, creativity and innovation. Collaboration across teams is a key component of our success.

Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design the next generation of MCU SOCs.

The team is working on several key IPs, in advanced Processes, for GP MCU and Security MCU SOCs, Some specific developments could be requested by customers linked with smartphone market.

You will be responsible to deliver clean layout view, this includes the following :

Working with circuit design team to plan / schedule work and negotiate any necessary layout trade-offs as needed to build complex analog layout in deep SubMicron CMOS technologies.

Recognize failure prone circuit and layout structures.

Running complete set of design verification tools available on Sub-Blocks and / or IP Level

Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.

Exceeding engineering specifications and expectations by working closely with the circuit design teams.

Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.


Education Level Required : BAC+5 (INGENIEUR,DESS,DEA...)

Strong Experiment in Analog Full Custom & Mixed Design, High Experiment in NVM IPs or Sensors will be appreciated; Strong Experiment in IPs Analog BE Flow ( from Floorplan to Packaging delivery)

Experience building tight matching, low capacitance, low power analog blocks, resistors, capacitors, high voltage devices, pad IOs, ESD structures, etc.

Proficient experience with custom and standard cell based floor planning and hierarchical layout assembly.

Deep understanding of IR drop, RC delay, electro-migration, self-heating and cross capacitance.

High-level proficiency in interpretation of Calibre, DRC, ERC, LVS, etc. reports.

Knowledge of MENTOR GRAPHICS or CADENCE layout tools.

Scripting experience in PERL or SKILL CODE is considered a plus, but not required.

Excellent communication skills and able to work with multi-functional teams.

Years of Work Experience : 0 to 5 years

Other skills required are : Virtuoso tools, Calibre DRC-LVS, PLS Extraction, IR-Drop Tools, STECCK(Calibre PERC) , Advanced Process Knowledge & Soft skills, as good communication, curiosity are required for this job

Candidate criteria

Education level required

5 - Master degree

Experience level required

01 / 06 / 2020

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