PhD Position F/M Automatic synthesis of multi-thread and out-of-order pipelines
Rennes, France
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Contexte et atouts du poste

This PhD offer is set within a collaboration between the PACAP and CAIRN Inria project-teams, and supported by the French National Research Agency (ANR).

It will combine the respective research expertises of CAIRN on compilers for high-level hardware synthesis and of PACAP on processor and GPU architecture.

The PhD will be co-advised by Caroline Collange (PACAP) and Steven Derrien (CAIRN). The PhD student will be administratively registered at the University of Rennes 1.

PhD thesis proposal

High-Level Synthesis (HLS) enables the generation of hardware circuits from imperative languages familiar to software programmers like C.

It is typically used to generate application-specific circuits on FPGAs using static pipelining. One main open challenge in HLS consists in efficiently handling conditional control flow and irregular dependencies.

Recent advances in speculative HLS techniques by the CAIRN team make a step toward flexible pipelining, by generating speculate-rollback mechanisms that are analogous to the branch prediction and memory dependence prediction techniques of general-purpose processors 1 .

In fact, we found that we could automatically synthesise a pipelined in-order processor core with branch prediction from a simple instruction set simulator written in C.

This preliminary work opens a new research direction at the intersection of hardware synthesis, compilers, and micro-architecture.

It will generalise advanced micro-architecture techniques that have been used only in processor design so far and make them available to any application using HLS.

In this direction, and capitalising on early results, the goal of this PhD is to extend high-level synthesis to generate automatically the micro-architectural features of modern processors and GPUs, such as hardware multi-threading and out-of-order execution.

At the language level, this will require introducing non-deterministic constructs, to select for instance which thread to advance next, or which instruction to execute from the reorder buffer, as these decisions will be deferred at execution time post-synthesis.

For instance, prior work have studied high-level synthesis of multi-threaded code, though the application has been limited so far to the avoidance of memory bank conflicts 2 .

At the compiler level, we will propose new code transformations to :

hoist all address calculations early in the simulator code (registers of the machine instruction),

generate hardware to check the dependencies between these addresses at runtime, based on techniques such as scoreboards, associative load / store queues or bloom filters,

generate a hardware scheduler that uses dependency information to select the next ready element (machine instruction) to process.

This will provide the basics for multi-thread and out-of-order execution. Looking forward, additional compiler transformations will be able to express out-of-order pipelines with register renaming, or GPUs with SIMT execution.

The outcome of the PhD will ease the development of custom embedded processors by synthesising them directly from a high-level description rather than require manual hardware design at the RTL level.

In addition, it will provide generic techniques for parallelising code with irregular dependencies. For instance, 3D graphics rendering pipelines involve out-of-order execution at a coarse granularity while guaranteeing primitive ordering semantics, and could benefit from these improvements in high-level synthesis optimisation 3 .


1 Steven Derrien, Thibaut Marty, Simon Rokicki, Tomofumi Yuki. Toward Speculative Loop Pipelining for High-Level Synthesis.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2020, 39 (11). https : / / / hal-02949516

2 Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason H. Anderson, and George A. Constantinides. 2019. EASY : Efficient Arbiter SYnthesis from Multi-threaded Code.

In Proceedings of the 2019 ACM / SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '19). Association for Computing Machinery, New York, NY, USA, 142 151.

DOI : https : / / / 10.1145 / 3289602.3293899

3 Kayvon Fatahalian and Mike Houston. 2008. A closer look at GPUs. Commun. ACM 51, 10 (October 2008), 50 57. DOI : https : / / doi.

org / 10.1145 / 1400181.1400197


Computer architecture, high-level synthesis, compilers

Principales activités

  • Conduct bibliographic study
  • Elaborate and discuss of new ideas
  • Implement ideas in an experimental compiler framework
  • Conduct performance evaluation and experimentation
  • Write scientific papers
  • Give research talks
  • Write a thesis manuscript
  • Compétences

    Technical skills and level required :

  • proficiency in C and C++ languages is required
  • knowledge of compiler design is highly valuable
  • experience in hardware synthesis and FPGA programming is a plus
  • Languages : English (C1 level or equivalent)

    Relational skills : ability to work in a team


  • Subsidized meals
  • Partial reimbursement of public transport costs
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